1. Technical Field
This invention relates generally to transactions, such as input/output (I/O) requests and their responses, and more particularly to serializing such transactions.
2. Description of the Prior Art
There are many different types of multi-processor computer systems. A symmetric multi-processor (SMP) system includes a number of processors that share a common memory. SMP systems provide scalability. As needs dictate, additional processors can be added. SMP systems usually range from two to 32 or more processors. One processor generally boots the system and loads the SMP operating system, which brings the other processors online. Without partitioning, there is only one instance of the operating system and one instance of the application in memory. The operating system uses the processors as a pool of processing resources, all executing simultaneously, where each processor either processes data or is in an idle loop waiting to perform a task. SMP systems increase in speed whenever processes can be overlapped.
A massively parallel processor (MPP) system can use thousands or more processors. MPP systems use a different programming paradigm than the more common SMP systems. In an MPP system, each processor contains its own memory and copy of the operating system and application. Each subsystem communicates with the others through a high-speed interconnect. To use an MPP system effectively, an information-processing problem should be breakable into pieces that can be solved simultaneously. For example, in scientific environments, certain simulations and mathematical problems can be split apart and each part processed at the same time.
A non-uniform memory access (NUMA) system is a multi-processing system in which memory is separated into distinct banks. NUMA systems are similar to SMP systems. In SMP systems, however, all processors access a common memory at the same speed. By comparison, in a NUMA system, memory on the same processor board, or in the same building block, as the processor is accessed faster than memory on other processor boards, or in other building blocks. That is, local memory is accessed faster than distant shared memory. NUMA systems generally scale better to higher numbers of processors than SMP systems.
Multi-processor systems usually include one or more memory controllers to manage memory transactions from the various processors. The memory controllers negotiate multiple read and write requests emanating from the processors, and also negotiate the responses back to these processors. Usually, a memory controller includes a pipeline, in which transactions, such as requests and responses, are input, and actions that can be performed relative to the memory for which the controller is responsible are output.
For transactions to be serviced correctly, usually they need to be serialized so that they are performed in the correct order. Serialization may occur within the pipeline of a memory controller, or prior to the transactions entering the pipeline. Transactions are commonly serialized by utilizing the cache addresses of memory lines to which they relate. This allows the serialization logic, for instance, to distinguish transactions from one another based on their addresses.
Typically, there is a serialization logic for each type of different transaction. For instance, non-coherent input/output (I/O)-related transactions may have one type of serialization logic, whereas coherent memory-related transactions may have another type of serialization logic. While this is a workable approach, it means that serialization logic must be developed for each type of different transaction, which can be time-consuming. Furthermore, space on an integrated circuit (IC) must be allocated for each developed serialization logic, which may be at a premium. For these and other reasons, therefore, there is a need for the present invention.